I. Field of the Disclosure
The technology of the disclosure relates generally to power multiplexing circuits configured to selectively supply power from multiple power rails to powered circuits.
II. Background
Circuits are increasingly being designed with power conservation in mind. This is particularly the case for portable electronic devices that are battery-powered. Common examples include mobile phones and laptop computers, among others. Increased power consumption undesirably results in faster battery drainage and shorter battery life. One method of conserving power is to lower an operating frequency of the circuit according to the active power equation P=CV2f. However, reducing the operating frequency results in lower circuit performance (i.e., speed). Another method of conserving power is to lower the operating voltage, since generally, active power reduces quadratically for a given reduction in operating voltage. However, lowering the operating voltage in a circuit lowers speed performance, which may also be undesirable. Further, certain cells or components of a circuit may have a minimum operating voltage below which they will not operate to read and write data, as well as retain data.
To address the tradeoff between performance and power consumption, multiple operating voltage domains (“voltage domains”) are increasingly being provided in circuits. Circuit paths are provided which pass through the multiple voltage domains to provide different operating voltages to different components of a circuit. Providing multiple voltage domains allows a lower voltage domain to provide power to components that do not require minimum voltage levels to conserve power. Components that either have a minimum operating voltage for memory operation functionality or provide critical paths where performance cannot be sacrificed may be powered by the higher voltage domain. Providing multiple voltage domains also allows the lower voltage domain to be scaled-down to conserve power during a power conservation mode, or scaled-up to provide for increased performance (i.e., hyper-performance), without affecting the operation of the components in the higher voltage domain.
In this regard, a power multiplexing system can be employed to selectively couple a power rail among multiple power rails each having different voltage domains (voltage levels) to supply power to a circuit. FIG. 1 is a block diagram of such an exemplary power multiplexing system 100. In the example power multiplexing system 100 in FIG. 1, a first power rail 102(1) and a second power rail 102(2) are provided. The first power rail 102(1) is coupled to first voltage source 104(1) at a first voltage VDD1. The second power rail 102(2) is coupled to a second voltage source 104(2) at a second voltage VDD2. The first and second voltage sources 104(1), 104(2) may be provided by the same or different power supplies (not shown). For example, the first voltage VDD1 may be 1.0 Volts (V) and the second voltage VDD2 may be 0.6 V. As an example, the power multiplexing system 100 may be configured to selectively couple the first power rail 102(1) or the second power rail 102(2) to an output power rail 105 coupled to a powered circuit 106 based on an operational mode of the powered circuit 106. For example, if the powered circuit 106 is a memory circuit, such as a memory array in a processor-based system, the power multiplexing system 100 may be configured to couple the first power rail 102(1) during active memory operations and couple the second power rail 102(2) to the output power rail 105 during an idle mode. For example, the voltage VDD2 may be sufficient for memory retention in the powered circuit 106.
With continuing reference to FIG. 1, the power multiplexing system 100 includes a first head switch 108(1) in the form of a P-type metal oxide semiconductor (PMOS) transistor 110(1). The PMOS transistor 110(1) is coupled between the first power rail 102(1) and the output power rail 105. The PMOS transistor 110(1) is configured to be activated and deactivated in response to a state of a first power rail enable signal 112(1) to couple and decouple, respectively the first power rail 102(1) to the output power rail 105. For example, if the first power rail enable signal 112(1) is a voltage of a logic ‘0’ vale, the PMOS transistor 110(1) is activated to couple the first power rail 102(1) to the output power rail 102(2). However, if the first power rail enable signal 112(1) is a voltage of a logic ‘1’ value, the PMOS transistor 110(1) is deactivated to decouple the first power rail 102(1) from the output power rail 102(2). The power multiplexing system 100 also includes second head switch 108(2), also in the form of a PMOS transistor 110(2), that is coupled between the second power rail 102(2) and the output power rail 105 to selectively couple and decouple the second power rail 102(2) to and from the output power rail 105 in response to a second power rail enable signal 112(2).
One problem with the power multiplexing system 100 in FIG. 1 is cross-conduction currents Icc flowing between the first power rail 102(1) at a higher voltage VDD1 to the second power rail 102(2) at a lower voltage VDD2. Cross-conduction currents Icc flow from the first power rail 102(1) to the second power rail 102(2) in this example when switching the coupling of the output power rail 105 from the first power rail 102(1) to the second power rail 102(2), and vice versa. Cross-conduction currents Icc cause various in-rush/out-rush currents due to limited impedances of the head switches 108(1), 108(2) causing issues such as device stress and power supply noise resulting in logic failures. Cross-conduction currents Icc also result in additional, wasted power consumption. Cross-conduction currents Icc can be avoided by ensuring that only one of the head switches 108(1), 108(2) is activated at a given time. For example, an active head switch 108(1), 108(2) can be turned off such that both the first and second head switches 108(1), 108(2) are turned off momentarily before turning on the other head switch 108(1), 108(2) to avoid cross-conduction currents Icc. However, if the leakage current on the output power rail 105 is too high, the voltage on the output power rail 105 may drop below a minimum retention or operating voltage of the powered circuit 106. Alternatively, the first and second head switches 108(1), 108(2) could be turned off and on with respect to each other quickly to limit the duration of the presence of the cross-conduction currents Icc. However, variance in capacitances on the first and second power rails 102(1), 102(2) and the output power rail 105 can cause charging that can drop the voltage VDD1, VDD2 at the first and second power rails 102(1), 102(2) and/or the output power rail 105, which may cause logic failures. The first and second power rails 102(1), 102(2) could be brought to substantially the same voltage to avoid cross-conduction currents Icc, but this results in additional power consumption.